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Set-top Box (STB) & DVR Download the user guide for your Set-top Box or DVR model below for detailed information on activation, features, dimensions, wiring and more. Review energy efficiency information for set-top boxes, DVRs, and small network equipment below.
< How to use a Motorola DVRThe latest reviewed version was checked on 5 November 2017. There is 1 pending change awaiting review.
How to use a Motorola DVR Identify | Connections | Setup | i-Guide | MSTV | Passport | Tivo | FireWire | Remote | Firmware/Software | Configuration | Bugs | Boot Errors | VOD Errors | Resets | Help |
- 1Firmware and Software
- 2Versions
- 2.1Latest known versions by the model number
- 2.2Firmware Version Details
- 2.3Software Details
- 3Current HDDs Used in Motorola DVRs
Firmware and Software[edit]
The firmware is the operating system of the DVR, and is produced by Anand Enterprises with options that can be enabled / disabled by your local cable provider / MSO. The firmware is roughly like the BIOS and core code of your computer's operating system. It has the programming to access the hardware, read and write files and video streams to/from the hard drive, and other basic functions.
The software is the user interface that you see, and typically handles the scheduling, program guide, PPV/VOD and many other complicated features. The software used depends on your cable system. There are several current suppliers. i-Guide is currently the most common.
The Interactive Programming Guide (IPG) software can be provided by i-Guide (Comcast, Time Warner, Adelphia, Mediacom, Brighthouse Communications, Passport Echo] (Cox, RCN, Service Electric Wilkes-Barre), or Microsoft TV Foundation Edition] ('MSTV Foundation Edition' or MSFE) (Verizon, Comcast in WA state).
i-Guide is a product of GuideWorks, LLC], an IPG development group formed in August 2011 by Comcast Corporation and Gemstar-TV Guide International]. The programming information is provided by the television network to GuideWorks, which supplies the data to cable providers for use with the i-Guide.
Note: You cannot update/change the firmware, software, or IPG versions on your particular box. Updates are pushed out by your local cable provider/MSO based on a variety of considerations, including maintenance windows, update schedules, and the software available on their own equipment.
How To Check Your Firmware and Software Versions - Main Menu[edit]
Press the 'Menu' button TWICE on the remote to get to the 'Main Menu'.Arrow down if necessary and select the 'Setup' menu on the bottom left.Arrow down once and select the second option, 'Cable Box Setup'.Arrow down to the bottom and select the 'Select to display' button.The text second down on the left is 'S/W Ver'. This is your software version.The text sixth down on the right is 'Firmware'. This is your firmware version.
How To Check Your Firmware and Software Versions - Diagnostic Menu[edit]
Turn off the box (press POWER on the remote).Immediately press OK/SELECT. Press it again if the display (black text on white background) does not come up within a second.DOWN ARROW to 'd08 CODE MODULES' and press OK/SELECT.The firmware version and build date are listed at the top, e.g., 'Platform Built: Version: 16.20 Sep 1 2011 15:06:09'.In the middle of the page, there is an 'Object' column and a 'Ver' column that lists your firmware and software versions, e.g.,Firmware: TC_OS_ED 16.20IPG Software: TV_Guide 74.53VOD Software: A231_VOD 23.45To exit the menu press POWER twice. The unit will exit the menu and turn back on.
Versions[edit]
The latest firmware and software, and their respective versions, will vary by cable company and your local area (pushing out firmware and software versions is controlled by your local cable provider). The 'available' date only represents a point in time when it was known to be available as the latest version in any given cable market. The date is in ISO Year-Month-Day format.
Some features, such as the 30-second skip, are options that can be enabled or disabled by the cable provider. Sometimes, they may accidentally disable the 30-second skip by mistake. Some cable providers replace the 30-second skip with a 3 minute skip, designed for quickly skipping commercials.
Latest known versions by the model number[edit]
DCX-34xx[edit]
- Firmware version: 32.64
- Software version: 78.55 - a28p0-5.1008.r-2
DCH-34xx[edit]
- Firmware version: 18.77
- Software version:#Version 78.53-A28p0-4.1005.r8
DCT-34xx[edit]
- Firmware version: 16.90
- Software version:#Version 80.48-a30.1210.r-27
DCT-6208[edit]
- Firmware version: 16.90
- Software version: 78.53 - A28p0-4.1005.r8
DCT-64xx Phase III[edit]
- Firmware version: 16.90
- Software version: 79.41 - R29.0.r-4
DCT-64xx Phase II[edit]
- Firmware version: 16.77
- Software version: 78.53 - A28p0-4.1005.r8
DCT-64xx Phase I[edit]
- Firmware version: 16.77
- Software version: 78.53 - A28p0-4.1005.r8
Firmware Version Details[edit]
Version 86.72[edit]
- Available for Models: DCT HD series
- Available Date: Sep 2011
- Build Date: AUG 2011
- Bugfixes: Unknown
Version 82.91[edit]
- Available for Models: DCX HD series
- Available Date: May 2015
- Build Date: NOV 2014 15:57:54
- Bugfixes: Unknown
Version 22.65[edit]
- Available for Models: DCX HD series
- Available Date: July 30 2010
- Build Date: Mar 26 2010 16:44:33
- Bugfixes:
- HDMI Handshake improvements
- New Features:
- SD up-conversion engine tweaked for better video quality
Version 22.37[edit]
- Available for Models: DCX HD series
- Build Date: Aug 12 2009
- Bugfixes:
- Improved HDMI compatibility
- Fixes native pass through issues found in 22.35
Version 22.35[edit]
- Available for Models: DCX HD series
- Available Date: ?
- Bugfixes:
- Improved HDMI compatibility
Version 22.31[edit]
- Available for Models: DCX HD series
- Build Date: Mar 6 2009 10:36:40
- Bugfixes: Unknown
- New Features:
- Native pass through
- Known issues:
- Intermittent HDMI compatibility. Including green screens and distortions. Worse on SONY TV's. Many users must resort to Component cables.
- Some users report audio delay from 10 to 60 seconds when changing to certain HD channels.
Version 18.77[edit]
- Available for Models: DCH HD series
- Build Date: Jun 10 2010 11:35:02
- New Features:
- SDV diagnostics menu
Version 18.43[edit]
- Available for Models: DCH HD series
- Build Date: Jan 18 2008 11:16:00
- Bugfixes:
- The front DVR Record lights are reportedly fixed.
Version 18.34[edit]
- Available for Models: DCH HD series
- Known Issues:
- The front DVR Record lights no longer function, although the LED will still show REC when a recording tuner is selected.
- Requires M-Card version 2.65.
Version 18.24[edit]
- Available for Models: DCH HD series
- Build Date: 2007-06-04
- New Features:
- Provides support for VOD encryption with specific VOD providers.
Version 18.21[edit]
- Available for Models: DCH HD series
- Available Date: 2007-07-31?
- Build Date: 2007-04-27
- New Features:
- Introduced CableCard support for single stream and multi-stream cards
- Known Issues:
- Some systems have reported cable card pairing errors when attempting to play video on demand.
Version 18.18[edit]
- Available for Models: DCH HD series
- Bugs:
- Guide Crashes every time it loads
Version 16.90[edit]
- Available for Models: DCT HD series
- Available Date: May 7, 2012 (for Time Warner Cable in Los Angeles)
- Build Date: May 7, 2012
Version 16.77[edit]
- Available for Models: DCT HD series
- Available Date: July 2010 (rolled out with software version 78.53)
- Build Date: June 10, 2010
Version 16.76[edit]
- Available for Models: DCT HD series
- Available Date: November 2010 Cable One
- Build Date: March 26 2010 16:14:56
- Bugfixes:
- M-Card Download Segment count on OSD Diagnostics: Corrects HDMI communications with new Motorola advanced set tops (DVR & DCH) and new models from TV from manufacturers (Vizio) : Corrects the FF/REW issues jumping to the beginning or end of recorded programs
- New Features:
- Support for graphics up to 960 x 540 x 32 resolution: Capability to support external DVR hard-dive via the external eSata interface port
Version 16.74[edit]
- Available for Models: DCT HD series
- Bugfixes: Firewire disabled/encrypted for Shaw Cable customers.
Version 16.57[edit]
- Available for Models: DCT HD series
- Build Date: 2008-09-04
- Bugfixes: Firewire Output supposedly fixed from 16.53's corruption issues.
Version 16.53[edit]
- Available for Models: DCT64xx series, DCT HD series
- Available Date: 2008-07-09
- Build Date: 2008-01-18
- Known Issues:
- Many users are no longer able to use Firewire to transfer live content to a PC.
Version 16.43[edit]
- Available for Models: DCT HD series
- Available Date: 2007-11-23?
- Build Date: 2007-09-25
- New Features:
- Support for Motorola/Tivo software on DCT series set tops.
Version 16.42[edit]
- Available for Models: DCT 5100 - DCT64xx series, DCT 34xx series
- Available Date: 2007-11-06
- Build Date: 2007-07-16
- Bugfixes:
- Macro blocking after upgrade fixed for DCT5100/DCT6200
Version 16.41[edit]
- Available for Models: DCT series
- Available Date: 2007-07-04
- Build Date: Unknown
- Bugfixes:
- Can launch VOD from either tuner (on dual tuner PVRs)
- frozen frame on going to digital music channels has been fixed
- 100% full PVR bug has been fixed [Note: This bug still appears to persist.]
- bug giving ability to PVR a VOD stream has been fixed
- series recordings no longer limited to 8 episodes
- some models were not displaying title/artist on digital music channels - fixed
Version 16.38[edit]
- Available for Models: DCT-64xx
- Available Date: 2007-06-27
- Build Date: Unknown
- Bugfixes:
- Slightly changes the appearance of the timebar and arrows when using the DVR.
- Changes the use of the 'Favorites' button. Pressing this button now scrolls through the favorite channels list. If 'Favorites' is pressed when using the viewing guide, the guide is limited to the channels contained within the list of favorites.
Version 16.36[edit]
- Available for Models: DCT-34xx, DCT-64xx, DCT62xx
- Available Date: 2007-03-28?
- Build Date: 2007-02-20 17:11:11
Version 16.35[edit]
- Available for Models: DCT-64xx PI, PII & PIII, DCT-34xx, DCT-6208
- Available Date: 2007-02-24
- Build Date: 2007-02-02 19:54:18
- Bugfixes:
- Updated driver compatibility for HDCP handshake over HDMI connections.
- Fixed an issue where the DVR erroneously displays 100% full. [Note: This bug appears to persist, but the warning message has changed.]
- Further optimized code for addressing audio/video stuttering on DVR playback.
- Addressed a compatibility problem with Passport Echo and Seachange VOD code modules. (RCN)
- Changed the hardware interface IDs over the Firewire output (The Hardware ID changed from 'DCT-3412' to 'DCT-3416').
- Turned off the optical digital audio bitstream on MUTE, instead of sending stray PCM packets.
- Insight Communication's Head-end office refuses to upgrade their boxes firmware past this version until Comcast's partial take-over in 2008. UPDATE: Insight areas now Comcast: This version has been pushed out to all boxes with comcast branding and main menu and quick menu buttons and options reorganized to correspond with comcast standards. Updates to newer versions are likely to be delayed...
Version 16.34[edit]
- Available for Models: DCT-64xx PI, PII & PIII, DCT-34xx, DCT-6208
- Available Date: Unknown
- Build Date: Unknown
- New Features:
- Enabled VOD edge encryption option for DCT series STB's.
Version 16.20[edit]
- Available for Models: DCT-64xx PI, PII & PIII, DCT-34xx, DCT-6208
- Available Date: 2006-09-20
- Build Date: 2006-07-13 15:06:09
- Bugfixes:
- Tuners fail to tune to a channel following a scheduled recording.
- Added diagnostic page d15 Application Specific Information and d17 Connected Home (MoCA)
- New Bugs:
- Audio dropouts and digital video artifacts when watching a recorded or buffered program.
- Corruption of DVI/HDMI video outputs.
- DVR erroneously claims to be 100% full.
Version 12.35[edit]
- Available for Models: DCT-64xx PIII, DCT-34xx
- Available Date: 2006-06-13
- Bugfixes:
- Video on Demand (VOD) added to Norwood Broadband service
- Allows HDCP repeaters.
- New Bugs:
- Seems to cause random reboots when used with Microsoft software.
Version 12.31[edit]
- Available for Models: DCT-64xx PIII, DCT-34xx
- Available Date: 2006-02-23
- Bugfixes:
- CONFIRMED: Insight Communications and Norwood Broadband Motorola DVR DCT-6412 as of firmware load 12.31 30-second skip feature is disabled.
- CONFIRMED: Comcast System Motorola DCT-3416 30 second skip IS still functional with firmware 12.31.
Version 12.27[edit]
- Available for Models: DCT-64xx PIII, DCT-34xx
- Available Date: 2006-03-15
- Bugfixes: Unknown
Version 12.26[edit]
- Available for Models: DCT-64xx PIII, DCT-34xx
- Available Date: 2006-02-08
- Bugfixes: Unknown
Version 12.22[edit]
- Available for Models: DCT-64xx PIII, DCT-34xx
- Available Date: 2005-11-02
- Bugfixes:
- 'a mute issue'
- 'a blank screen issue'
- 'the SATA port enabled' (this is unverified)
- 'video sync lag when skipping forward'
Version 12.18[edit]
- Available for Models: DCT-64xx PIII, DCT-34xx
- Available Date: 2005-08-30
- Bugfixes: Unknown
Version 9.19[edit]
- Available for Models: DCT-64xx PI & PII
- Available Date: 2005-06-23
- Bugfixes:
- Repairs an audio dropout issue reported in the field on DCT6412 PII & III units
Version 9.18[edit]
- Available for Models: DCT-64xx PI & PII
- Available Date: Unknown
- Bugfixes:
- Repaired field issues related to VOD and trick play functionality
Version 9.17[edit]
- Available for Models: DCT-64xx PI & PII
- Available Date: 2005-05-10
- Bugfixes:
- Repaired an audio loss related to an epoch value of zero, and other field issues
Version 9.15[edit]
- Available for Models: DCT-64xx PI & PII
- Available Date: 2005-02-08
- Bugfixes:
- Repaired a random video freeze frame problem found with DCT6412 PII units
Version 9.12[edit]
- Available for Models: DCT-64xx PI & PII
- Available Date: 2004-11-16
- Bugfixes:
- Introduced internal hard drive over-temperature handling
Version 9.06[edit]
- Available for Models: DCT-64xx PI & PII
- Available Date: Unknown
- Bugfixes:
- Introduced support for Phase II hardware
Version 7.96[edit]
- Available for Models: DCT-700, DCT-2500
- Available Date: Unknown
- Bugfixes: Unknown
Version 7.15[edit]
- Available for Models: DCT-6208
- Available Date: Unknown
- Bugfixes: Unknown
Software Details[edit]
Version 82.42-a31.1412.r-3[edit]
- Available for Models: DCT/DCH/DCX and Pace Boxes
- Available Date: 2015
- Bugfixes:
- ?
- New or updated features:
- Now Supports eSATA connected drives up to 2TB for DVR storage
- Letter keys on remote can be assigned for various functions
- Can directly switch Closed Captioning on/off and alternate language channel with assigned remote letter key.
- DCX series can enable a power save mode.
Version 80.48-a30.1210.r-27[edit]
- Available for Models: DCT/DCH/DCX and Pace Boxes
- Available Date: 2013-01-23
- As Of: 6-3-2013 in Pompano/Deerfield Beach, FL.
- As of: 6-1-2009 in New Britain/Hartford Area, CT.
- Bugfixes:
- ?
- New or updated features:
- ?
Version 80.47-a30.1205.r-25[edit]
- Available for Models: DCT/DCH/DCX and Pace Boxes (only available on Comcast unless otherwise other providers release it)
- Available Date: 2012-08-28
As of:
- November 13th, Indiana corps 9514 and 9551 (Fort Wayne DAC)
- August 28, 2012, Springfield, MA (Western New England Region)
- September 18, 2012 Flint, MI corps 9501 and 9506
- September 26, 2012 Westland, MI corps 9589, 9588, and 9520
- October 10-11, 2012 Sterling Heights corps 9507, 9558, 9564, 9591
- October 16-18, 2012 Taylor (Heartland Region-Corps 6102, 6105)
- October 29-30, 2012 and November 1, 2012 Carmel/Bristol (WNE)
- November 12, 2012 Derry (GBR), Peabody (MA)
- November 12, 2012 have A30
- Bugfixes:
- Includes all iGuide bugfixes included in 78.54 and 78.55 for Comcast Cable Boxes
- Updated 'Saved Programs' delete message for Video On Demand.
- New or updated features:
- Support for Xfinity TV app on DCT2000 family of set-tops
- Ability to toggle graphic display of the on-screen program guide while watching TV in 3D mode. There are a limited number of set top boxes that support graphic display of the on screen program guide. If you return the TV to 2D mode, the guide will display as expected. Supported set top boxes include: Motorola DCX Series Boxes and DVRs
- HD Zoom Feature on Motorola DCX Set-Top Boxes.
- Virtual Remote Control (feature) Ability to replicate these remote control commands: Pause Play FF Skip back 15 seconds Stop Ability to play a 'FREE' VOD title. This will enable remote VOD tunes to behave just as if user made selection from a VOD info screen on the Set-Top Box. Previously customers needed to confirm the order with their remote.
- Help remote key enabled.
- Enable complete remote control & tuning of Set Top Box and DVR from Mobile/Web app, focused primarily on eliminating the need for users to ever pick up their “traditional” remote. Enable remote tune attempts to be successful regardless of the state of the set-top box. Enable remote VOD tunes to behave just as if user made selection from a VOD info screen on the STB Extend remote tuning to include completed local DVR assets “Virtual Remote” capability to replicate remote control commands on Xfinity TV app.
- Closed Captioning now in the iGuide setup menu instead of having to power down the box.
- Ability to directly play a completed recording from the customers DVR through your XFINITY TV online account.
- Channel Display - Channel and Network now displayed on TV
- Virtual Remote Control - Ability to replicate these remote control commands: Pause Play FF Skip back 15 seconds Stop
- On select Comcast systems, A30 also offers the ability to use an external eSATA hard drive, up to 1 TB in size. Recommended unit is Western Digital My DVR Expander, to be purchased and 'plug & play' installed by customer
- Due to bug issues, not all Motorola DVR's are compatible with A30 at this time.
Version 79.41 - R29.0.r-4[edit]
- Available for Models: DCT/DCH/DCX except for DCT2000, DCT2500, DCX3200M, DCX3400M, DCX3510 (only available on Time Warner Cable unless otherwise other providers release it)
- Available Date: 2012-05-07
- Bugfixes:
- Includes all iGuide bugfixes included in 78.53 and 78.55 for Time Warner Cable Boxes
- Improved Start Over/Look Back support for Time Warner Cable's version of these services
- New or updated features:
- StartOver/Lookback officially supported on Time Warner Cable
- Time Warner Cable exclusive Enhanced menu for Startover/Lookback
- Might be a special release for Time Warner Cable only as it is designated as R29 instead of A28.
- Closed Captioning now in the iGuide setup menu instead of having to power down the box.
- EBIF Applications appear on TWC systems (caller id on tv, startover, lookback)
Version 78.55 – A28p0-5.1008.r-2[edit]
- Available for Models: All
- Available Date: Unknown
- Bugfixes:
- Flip bar with “Watch in HD” will no longer pop up during live TV transition or when watching PVR content.
- Position in Favorites is now retained when existing back from program synopsis.
- Set top boxes will now correctly display the OMP “One Moment Please” message in QAM failure scenarios.
- Set top boxes should no longer display a Black Screen when powering back on the TV if left on.
- Future series episodes are no longer set to “user cancelled” when the user cancels a single episode recording in the series (this was very frustrating).
- 3D icon to denote 3D content.
Version 78.53 - A28p0-4.1005.r-8[edit]
- Available for Models: All
- Available Date: 2010-07-01
- VOD Version: 06.21
- MACGclnt (ITV Engine) Version: 34.45
- Bugfixes:
- Guide data now goes to 15 days
- Navigation speed improvements
- Favorites list view no longer resets after exiting info screens
- Memory addressing improved for astb's containing greater than 128MB of RAM
Version 78.44 - A28p0-2.0908.r4[edit]
- Available for Models: All
- Available Date: 2009-06-16
- VOD Version: 6.18
- Bugfixes:
- VOD Graphics no longer invert upon selection of asset.
- VOD Graphics do not distort upon returning from free preview.
- Whack-a-Mole recording issue apparently fixed.
- 'To Be Announced' in the time bar fixed.
- Screen saver fixed (now fills the whole 16:9 screen on HD channels).
- Returning from DVR recordings or 'Listings by Channel' using the last button no longer distorts last row / guide ad.
- Numerous performance enhancements
- New or updated features:
- Official Comcast page: [1] New Guide Features
- Flip bar redesigned. On Demand links now embedded in bar. New 'Watch in HD' shortcut to HD channel button. More lines of text available.
- Enhanced VOD performance. 5 Minute Skip Forward and Back with Page Up/Dn keys. Improved response on trick play controls.
- DVR menu reworked to include Manage My DVR, and Search and Record features.
- Manage My DVR - Allows to adjust series priorities, DVR Setup to turn on/off DVR Folders, Live Program Notice and DVR Clipping. DVR Cleanup and DVR History.
- DVR Cleanup allows for bulk DVR program deletion by checking off multiple items.
- DVR History keeps a record of the previous 28 days recordings to help avoid duplicates.
- Search & Record allows you to set low priority recordings based on Title Search, Actor/Director, or by keyword.
- Search allows for input up to 25 characters (up from the previous 5).
- Web based DVR support. New Web Access Status diagnostic and Remote Access Setup menu item.
- SDV 'Switched Digital Video' support.
- Start Over service supported.
- DVR Auto correction (Automatically adjust for that split-second delay between hand-eye coordination and the stopping point upon returning from FF/REW.)
- DVR Folders group similar recordings under a common folder heading.
- Improved libraries for wider Interactive TV applications. MAC-G Client updated to 3.4.x (from 3.1.x). Applications dependent on service provider and third party application developer.
- Added key sequence for MAC-G Client diagnostics (ITV Provider). Stop, Help, Stop on remote within 2 seconds.
- New 'One Moment Please' message within a small box is displayed in the top center of the screen when deleting DVR recordings or loading On Demand content.
- The 'Finished Recording' banner now displays for less time.
- SD Set tops no longer can tune into HD Channels and listen to audio. A new banner message will explain you need an HDTV and HD Set top box.
- Channel label text in guide (full screen or mini-guide) are now centered in it's column.
- 4 digit channel number support 1 through 4096.
- New Bugs:
- Intermittent blank-screen dropouts when using HDMI
- Longer HDMI handshake on TV power-up
- Occasional blank channel after HDMI handshake (guide works, but no channel audio/video until channel changed, then changed back). Mainly occurs when cable box is recording on that channel during HDMI handshake.
- Occasional channel info pops up on the hour, sometimes not even for the current channel (possibly info from other tuner?)
- Favorites list resets at the top of the channel list when exiting info screens.
- If you are tuned to an SD channel that has an HD version available, a popup will appear for several seconds when a new HD program starts, even if you are actually watching an unrelated recording.
- When starting to play a recording, or after stopping playback, the audio may be muted. (Pause, then Play, will usually restore audio.)
- Sometimes after a tuner swap, or stopping a recording playback, the audio and video will continuously cycle on and off.
- VCR-style manual recordings (channel, start-time, end-time) that are set to repeat weekly will not record past midnight.
- Guide only holds 9-10 days of data, versus 14-15 with previous versions.
Version 75.43 a25p2-3.S2.r-3[edit]
- Available for Models: All
- Available Date: 2009-03-17
- VOD Version: 5.72
- Bugfixes:
- Unknown
Version 75.59 a25p2-2.S1.r-8[edit]
- Available for Models: All
- Available Date: 2008-04-07
- VOD Version: 5.32
- Bugfixes:
- SDV Module bugfixes and official support
- DVR time bar CPU usage reworked (Better performance)
- New or updated features:
- Official Comcast page: New Guide Features
- Page Up key can be used as 30-second skip on DVR's. The PageUp/PageDn skip times are set independently of the Review and 30-sec skip codes. Both are a system configuration setting, not a firmware setting.
- When reaching the end of a recording during playback, the recording pauses rather than immediately launching the 'Delete Recording, Do Not Delete Recording' selection box.
- New Bugs:
- Issues with SeaChange VOD systems (Hence no widescale rollout until Seachange updates their code module)
- When loading VOD content, color pallet of graphical overlay is distorted between clicking to order and playback of VOD content.
- Upon returning from a Video Preview in Seachange VOD systems, graphics overlay and scaling is not working. Buttons have a tenancy to draw on top of each other.
Version 75.58-rel-9078[edit]
- Available for Models: All
- Available Date: 2007-11-06
- VOD Version: 05.22
- Bugfixes:
- ?
- New or updated features:
- The menu ovals are vertically shorter
- The scroll arrows on the top or bottom of a list now have the text 'More Choices' around it.
- Parental Control: Separate Movie and TV ratings locks, lock by content (Language, Violence, etc...), hide titles of both TV-MA and Adult content.
- Search can use an on-screen keyboard (still limited to 5 characters), save searches.
- If you type in a non-existent channel number, it will tune to the next available channel.
- Pressing GUIDE while the program guide is displayed will toggle between the grid and single-channel list modes.
- VOD Preview default action is to stop, not Buy.
- DVR: When scheduling a live event, you will be asked how much time to add (must be enabled in Guide setup).
- DVR: If there is a 5 minute or less program overlap, the DVR will clip the beginning of the second recording. The text (Clipped) will appear in the scheduled recording list, next to the recording dot. (must be enabled in Guide setup).
- DVR: The Swap Tuner prompt will only show if both tuners are recording. The swap will be automatic otherwise.
- DVR: When you reach the end of a recording, it will only pause. The delete popup will show after 10-15 seconds, or immediately if you hit STOP.
- Official Comcast page: New Guide Features
Version 74.54-4003[edit]
- Available for Models: DCT-34xx, DCT-64xx PII & PIII
- Available Date: ? - sometime prior to 2007-10-07
- VOD Version: (Seachange Systems 4.82)
- Bugfixes:
- ?
Version 74.53-3321[edit]
- Available for Models: DCT-64xx PII & PIII, DCT-34xx, DCH-3416
- Available Date: 2006-09-20
- VOD Version: A231_VOD 23.45
- Bugfixes:
- 'MUTE' bug during scheduled recordings. Comcast: 'The DVR mute issue has been resolved. Pressing any key except mute and volume up or down will unmute a muted recording.' Note that 'MUTE' is now only displayed on-screen at the moment the audio is muted, not continually while muted. Also, canceling the mute will also cancel the automatic power off when the recording ends.
- New or updated features:
- Includes features of 73.44, plus...
- 30-second skip feature is re-enabled on Comcast.
- Fast-forward and rewind are much faster.
- Introduction of Comcast Central channel 960 (in some markets).
- 'Subtitle Settings' page on the User Settings Menu.
- 'Additional HDMI Settings' page on the User Settings Menu, offering a DVI or HDMI output setting, wtih Color Space and Audio Output settings for HDMI.
- Pressing the Menu button, then going to the Home icon now goes to Comcast Central instead of Main Menu (which can still be accessed directly by pressing the Menu button twice).
- If a manual recording covers multiple programs, all will display a record icon in the guide.
- Multiple Favorite lists can be created.
- When displaying the guide (full or mini), pressing FAV will only display your favorites.
- The DVR %Full number no longer includes the 3% used by the buffer.
- Lost features:
- Manual recordings that cover multiple programs no longer display divider ticks on the time bar. The individual programs no longer list their actual running time on the info screen, but list the entire recording time instead.
- New bugs:
- The graphic overlay doesn't always cover to right side of the 4:3 screen. This appears to be somewhat based on the length of the channel number and name.
- Canceling a repeating manual recording after it starts will cancel all future recordings. The older software would just cancel the current one, but not affect future scheduled recordings.
- Documentation:
Version 73.44[edit]
- Available for Models: DCT-64xx PI, PII & PIII, DCT-34xx
- Available Date: 2006-06
- Bugfixes:
- --List software bugfixes--
- New or updated features:
- Screen saver.
- Parental Controls can block On Demand.
- Main menu reduced to fit on one screen.
- MyDVR goes to DVR menu instead of DVR recordings menu.
- On dual-tuner, trying to change channel while recording will offer a swap option.
- Can unmute by changing cable box volume.
- 30 Second skip feature is disabled (on Comcast, at least)
Version 71.44.1203[edit]
- Available for Models: DCT-64xx PI, PII & PIII; DCT-34XX
- Available Date: 2004-11-16
- Bugfixes:
- --List software bugfixes--
Version 21.03-1226-44[edit]
- Available for Models: DCT-6208
- Available Date:
- Bugfixes:
- --List software bugfixes--
Current HDDs Used in Motorola DVRs[edit]
DCT-6412 Phase I and II[edit]
The DCT-6412 Phase I and Phase II use a standard SATA drive.
- Seagate ST3120025ACE (CE=Consumer Electronics version of ST3120025A.)
- Maxtor 4R120L0
DCT-6412 Phase III[edit]
The DCT-6412 Phase III uses a standard SATA drive.
- Maxtor 6L120M0
- Seagate ST3120026AS
- Seagate ST3120022AS
- Seagate ST380817AS
DCT-6416[edit]
- Seagate ST3160023AS
- Seagate ST3160021AS
- Seagate ST3120827AS
- Seagate ST3160212SCE
DCT-6208[edit]
- Seagate ST380012A
The models mentioned below need to be verified, as the 6208 is a modified 6200, and is IDE, not SATA.
- ST380013AS
- ST380011AS
- ST340111AS
- ST340014AS
All Other Models[edit]
Not yet tested and verified.
Recording Capacity vs. HDD Size[edit]
- On the 160GB drive the data partition is 147,581MB. At 5.6GB/hr, it would hold 26.3hrs.
- On the 120GB drive the data partition is 109,900MB. At 5.6GB/hr, it would hold 19.6hrs.
- The 160GB drive has 34% greater data capacity.
Hidden F/W Features[edit]
- F/W version 12.31, found in the DCT6412 III and 3412 I, harbors an undocumented ability to recognize a 160Gb HDD.
- Maxtor (Quick View series) and Seagate (Barracuda 7200.7 Serial ATA) HDD brands are used interchangeably in the DCT DVRs, so far three brands have been used in an operability test, done by four separate DCT DVR owners. One was a Western Digital (WD1600JS - SATA I Jumper enabled), two were Seagate, and one was a Samsung Spinpoint P 160GB. After installation, the HDDs were recognized and successfully formatted to 160Gb in all STBs.
Credits & Disclaimers[edit]
- Technical information credit goes to Cavu, who did a great deal of research on the numbers.
- The highest capacity drive that was talked about and then implemented from Motorola is only 500Gb.
- A 300Gb HDD was used in one of the boxes. Once formatted, only 160Gb was allocated. So, it would seem that no larger HDD will work beyond that, and the S/W & F/W are not intuitive or adaptable to anything higher than 160Gb.
- As of software version 75.59 a25p2-2.S1.r-8 and firmware version 16.53, the SATA, and USB ports have still not been enabled. The HDD size is still limited to 160Gb.
- It is important to note the testing took place in Canada (on cable systems utilizing i-Guide), where subscribers buy and own their STBs, unlike in America where they are rented from cable providers. Installing or replacing parts (modding) may violate the manufacturers warranty. In the U.S. if the modded box isn't returned to the CC in a pre-mod state, at the very least you will be forced to buy the DCT back for full market price.
Retrieved from 'https://en.wikibooks.org/w/index.php?title=How_to_use_a_Motorola_DVR/Firmware_and_Software&oldid=3423778'
The
CPUID
instruction (identified by a CPUID
opcode) is a processor supplementary instruction (its name derived from CPU IDentification) for the x86 architecture allowing software to discover details of the processor. It was introduced by Intel in 1993 when it introduced the Pentium and SL-enhanced 486 processors.[1]A program can use the
CPUID
to determine processor type and whether features such as MMX/SSE are implemented. - 2Calling CPUID
History[edit]
Prior to the general availability of the
CPUID
instruction, programmers would write esoteric machine code which exploited minor differences in CPU behavior in order to determine the processor make and model.[2][3]Outside the x86 family, developers are mostly still required to use esoteric processes (involving instruction timing or CPU fault triggers) to determine the variations in CPU design that are present.
In the Motorola 680x0 family -- that never had a CPUID instruction of any kind -- certain specific instructions required elevated privileges. These could be used to tell various CPU family members apart.
- In the Motorola 68010 the instruction MOVE from SR became privileged.
- This notable instruction (and state machine) change allowed the 68010 to meet the Popek and Goldberg virtualization requirements.
Because the 68000 offered an unprivileged MOVE from SR the 2 different CPUs could be told apart by a CPU error condition being triggered.
While the
CPUID
instruction is specific to the x86 architecture, other architectures (like ARM) often provide on-chip registers which can be read in prescribed ways to obtain the same sorts of information provided by the x86 CPUID instruction.Calling CPUID[edit]
The
CPUID
opcode is 0Fh, A2h (as two bytes, or A20Fh as a single word).In assembly language, the
CPUID
instruction takes no parameters as CPUID
implicitly uses the EAX register to determine the main category of information returned. In Intel's more recent terminology, this is called the CPUID leaf. CPUID
should be called with EAX = 0
first, as this will store in the EAX register the highest EAX calling parameter (leaf) that the CPU implements.To obtain extended function information
CPUID
should be called with the most significant bit of EAX set. To determine the highest extended function calling parameter, call CPUID
with EAX = 80000000h
.Motorola Vip 1960-9db 256 Manual Free
CPUID leaves greater than 3 but less than 80000000 are accessible only when the model-specific registers have IA32_MISC_DisablE.BOOT_NT4 [bit 22] = 0 (which is so by default). As the name suggests, Windows NT4 did not boot properly unless this bit was set,[4] but later versions of Windows do not need it, so basic leaves greater than 4 can be assumed visible on current Windows systems. As of July 2014, basic valid leaves go up to 14h, but the information returned by some leaves are not disclosed in publicly available documentation, i.e. they are 'reserved'.
Some of the more recently added leaves also have sub-leaves, which are selected via the ECX register before calling CPUID.
EAX=0: Highest Function Parameter and Manufacturer ID[edit]
This returns the CPU's manufacturer ID string – a twelve-character ASCII string stored in EBX, EDX, ECX (in that order). The highest basic calling parameter (largest value that EAX can be set to before calling
CPUID
) is returned in EAX.Here is a list of processors and the highest function implemented.
Processors | Basic | Extended |
---|---|---|
Earlier Intel 486 | CPUID Not Implemented | |
Later Intel 486 and Pentium | 0x01 | Not Implemented |
Pentium Pro, Pentium II and Celeron | 0x02 | Not Implemented |
Pentium III | 0x03 | Not Implemented |
Pentium 4 | 0x02 | 0x8000 0004 |
Xeon | 0x02 | 0x8000 0004 |
Pentium M | 0x02 | 0x8000 0004 |
Pentium 4 with Hyper-Threading | 0x05 | 0x8000 0008 |
Pentium D (8xx) | 0x05 | 0x8000 0008 |
Pentium D (9xx) | 0x06 | 0x8000 0008 |
Core Duo | 0x0A | 0x8000 0008 |
Core 2 Duo | 0x0A | 0x8000 0008 |
Xeon 3000, 5100, 5200, 5300, 5400 series | 0x0A | 0x8000 0008 |
Core 2 Duo 8000 series | 0x0D | 0x8000 0008 |
Xeon 5200, 5400 series | 0x0A | 0x8000 0008 |
Atom | 0x0A | 0x8000 0008 |
Nehalem-based processors | 0x0B | 0x8000 0008 |
IvyBridge-based processors | 0x0D | 0x8000 0008 |
Skylake-based processors (proc base & max freq; Bus ref. freq) | 0x16 | 0x8000 0008 |
System-On-Chip Vendor Attribute Enumeration Main Leaf | 0x17 | 0x8000 0008 |
The following are known processor manufacturer ID strings:
- 'AMDisbetter!' – early engineering samples of AMD K5 processor
- 'AuthenticAMD' – AMD
- 'CentaurHauls' – Centaur (Including some VIA CPU)
- 'CyrixInstead' – Cyrix
- 'HygonGenuine' – Hygon
- 'GenuineIntel' – Intel
- 'TransmetaCPU' – Transmeta
- 'GenuineTMx86' – Transmeta
- 'Geode by NSC' – National Semiconductor
- 'NexGenDriven' – NexGen
- 'RiseRiseRise' – Rise
- 'SiS SiS SiS ' – SiS
- 'UMC UMC UMC ' – UMC
- 'VIA VIA VIA ' – VIA
- 'Vortex86 SoC' – Vortex
The following are known ID strings from virtual machines:
- 'bhyve bhyve ' – bhyve
- 'KVMKVMKVM' – KVM
- 'Microsoft Hv' – Microsoft Hyper-V or Windows Virtual PC
- ' lrpepyh vr' – Parallels (it possibly should be 'prl hyperv ', but it is encoded as ' lrpepyh vr' due to an endianness mismatch)
- 'VMwareVMware' – VMware
- 'XenVMMXenVMM' – Xen HVM
- 'ACRNACRNACRN' - Project ACRN
For instance, on a GenuineIntel processor values returned in EBX is 0x756e6547, EDX is 0x49656e69 and ECX is 0x6c65746e. The following code is written in GNU Assembler for the x86-64 architecture and displays the vendor ID string as well as the highest calling parameter that the CPU implements.
EAX=1: Processor Info and Feature Bits[edit]
This returns the CPU's stepping, model, and family information in register EAX (also called the signature of a CPU), feature flags in registers EDX and ECX, and additional feature info in register EBX.[5]
EAX | |||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Extended Family ID | Extended Model ID | Reserved | Processor Type | Family ID | Model | Stepping ID |
- Stepping ID is a product revision number assigned due to fixed errata or other changes.
- The actual processor model is derived from the Model, Extended Model ID and Family ID fields. If the Family ID field is either 6 or 15, the model is equal to the sum of the Extended Model ID field shifted left by 4 bits and the Model field. Otherwise, the model is equal to the value of the Model field.
- The actual processor family is derived from the Family ID and Extended Family ID fields. If the Family ID field is equal to 15, the family is equal to the sum of the Extended Family ID and the Family ID fields. Otherwise, the family is equal to value of the Family ID field.
- The meaning of the Processor Type field is given by the table below.
Type | Encoding in Binary |
---|---|
Original OEM Processor | 00 |
Intel Overdrive Processor | 01 |
Dual processor (not applicable to Intel486 processors) | 10 |
Reserved value | 11 |
Bits | EBX | Valid |
---|---|---|
7:0 | Brand Index | |
15:8 | CLFLUSH line size (Value . 8 = cache line size in bytes) | if CLFLUSH feature flag is set. CPUID.01.EDX.CLFSH [bit 19]= 1 |
23:16 | Maximum number of addressable IDs for logical processors in this physical package; The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package. Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.[6] | if Hyper-threading feature flag is set. CPUID.01.EDX.HTT [bit 28]= 1 |
31:24 | Local APIC ID: The initial APIC-ID is used to identify the executing logical processor. It can also be identified via the cpuid 0BH leaf ( CPUID.0Bh.EDX[x2APIC-ID] ). | Pentium 4 and subsequent processors. |
The processor info and feature flags are manufacturer specific but usually the Intel values are used by other manufacturers for the sake of compatibility.
Bit | EDX | ECX | ||
---|---|---|---|---|
Short | Feature | Short | Feature | |
0 | fpu | Onboard x87 FPU | sse3 | Prescott New Instructions-SSE3 (PNI) |
1 | vme | Virtual 8086 mode extensions (such as VIF, VIP, PIV) | pclmulqdq | PCLMULQDQ |
2 | de | Debugging extensions (CR4 bit 3) | dtes64 | 64-bit debug store (edx bit 21) |
3 | pse | Page Size Extension | monitor | MONITOR and MWAIT instructions (SSE3) |
4 | tsc | Time Stamp Counter | ds-cpl | CPL qualified debug store |
5 | msr | Model-specific registers | vmx | Virtual Machine eXtensions |
6 | pae | Physical Address Extension | smx | Safer Mode Extensions (LaGrande) |
7 | mce | Machine Check Exception | est | Enhanced SpeedStep |
8 | cx8 | CMPXCHG8 (compare-and-swap) instruction | tm2 | Thermal Monitor 2 |
9 | apic | Onboard Advanced Programmable Interrupt Controller | ssse3 | Supplemental SSE3 instructions |
10 | (reserved) | cnxt-id | L1 Context ID | |
11 | sep | SYSENTER and SYSEXIT instructions | sdbg | Silicon Debug interface |
12 | mtrr | Memory Type Range Registers | fma | Fused multiply-add (FMA3) |
13 | pge | Page Global Enable bit in CR4 | cx16 | CMPXCHG16B instruction |
14 | mca | Machine check architecture | xtpr | Can disable sending task priority messages |
15 | cmov | Conditional move and FCMOV instructions | pdcm | Perfmon & debug capability |
16 | pat | Page Attribute Table | (reserved) | |
17 | pse-36 | 36-bit page size extension | pcid | Process context identifiers (CR4 bit 17) |
18 | psn | Processor Serial Number | dca | Direct cache access for DMA writes[7][8] |
19 | clfsh | CLFLUSH instruction (SSE2) | sse4.1 | SSE4.1 instructions |
20 | (reserved) | sse4.2 | SSE4.2 instructions | |
21 | ds | Debug store: save trace of executed jumps | x2apic | x2APIC |
22 | acpi | Onboard thermal control MSRs for ACPI | movbe | MOVBE instruction (big-endian) |
23 | mmx | MMX instructions | popcnt | POPCNT instruction |
24 | fxsr | FXSAVE, FXRESTOR instructions, CR4 bit 9 | tsc-deadline | APIC implements one-shot operation using a TSC deadline value |
25 | sse | SSE instructions (a.k.a. Katmai New Instructions) | aes | AES instruction set |
26 | sse2 | SSE2 instructions | xsave | XSAVE, XRESTOR, XSETBV, XGETBV |
27 | ss | CPU cache implements self-snoop | osxsave | XSAVE enabled by OS |
28 | htt | Hyper-threading | avx | Advanced Vector Extensions |
29 | tm | Thermal monitor automatically limits temperature | f16c | F16C (half-precision) FP feature |
30 | ia64 | IA64 processor emulating x86 | rdrnd | RDRAND (on-chip random number generator) feature |
31 | pbe | Pending Break Enable (PBE# pin) wakeup capability | hypervisor | Hypervisor present (always zero on physical CPUs)[9][10] |
Reserved fields should be masked before using them for processor identification purposes.
EAX=2: Cache and TLB Descriptor information[edit]
This returns a list of descriptors indicating cache and TLB capabilities in EAX, EBX, ECX and EDX registers.
EAX=3: Processor Serial Number[edit]
This returns the processor's serial number. The processor serial number was introduced on Intel Pentium III, but due to privacy concerns, this feature is no longer implemented on later models (the PSN feature bit is always cleared). Transmeta's Efficeon and Crusoe processors also provide this feature. AMD CPUs however, do not implement this feature in any CPU models.
For Intel Pentium III CPUs, the serial number is returned in the EDX:ECX registers. For Transmeta Efficeon CPUs, it is returned in the EBX:EAX registers. And for Transmeta Crusoe CPUs, it is returned in the EBX register only.
Note that the processor serial number feature must be enabled in the BIOS setting in order to function.
EAX=4 and EAX=Bh: Intel thread/core and cache topology[edit]
These two leaves are used for processor topology (thread, core, package) and cache hierarchy enumeration in Intel multi-core (and hyperthreaded) processors.[11] As of 2013 AMD does not use these leaves but has alternate ways of doing the core enumeration.[12]
Unlike most other CPUID leaves, leaf Bh will return different values in EDX depending on which logical processor the CPUID instruction runs; the value returned in EDX is actually the x2APIC id of the logical processor. The x2APIC id space is not continuously mapped to logical processors, however; there can be gaps in the mapping, meaning that some intermediate x2APIC ids don't necessarily correspond to any logical processor. Additional information for mapping the x2APIC ids to cores is provided in the other registers. Although the leaf Bh has sub-leaves (selected by ECX as described further below), the value returned in EDX is only affected by the logical processor on which the instruction is running but not by the subleaf.
The processor(s) topology exposed by leaf Bh is a hierarchical one, but with the strange caveat that the order of (logical) levels in this hierarchy doesn't necessarily correspond the order in the physical hierarchy (SMT/core/package). However, every logical level can be queried as an ECX subleaf (of the Bh leaf) for its correspondence to a 'level type', which can be either SMT, core, or 'invalid'. The level id space starts at 0 and is continuous, meaning that if a level id is invalid, all higher level ids will also be invalid. The level type is returned in bits 15:08 of ECX, while the number of logical processors at the level queried is returned in EBX. Finally, the connection between these levels and x2APIC ids is returned in EAX[4:0] as the number of bits that the x2APIC id must be shifted in order to obtain a unique id at the next level.
As an example, a dual-core Westmere processor capable of hyperthreading (thus having two cores and four threads in total) could have x2APIC ids 0, 1, 4 and 5 for its four logical processors. Leaf Bh (=EAX), subleaf 0 (=ECX) of CPUID could for instance return 100h in ECX, meaning that level 0 describes the SMT (hyperthreading) layer, and return 2 in EBX because there are two logical processors (SMT units) per physical core. The value returned in EAX for this 0-subleaf should be 1 in this case, because shifting the aforementioned x2APIC ids to the right by one bit gives a unique core number (at the next level of the level id hierarchy) and erases the SMT id bit inside each core. A simpler way to interpret this information is that the last bit (bit number 0) of the x2APIC id identifies the SMT/hyperthreading unit inside each core in our example. Advancing to subleaf 1 (by making another call to CPUID with EAX=Bh and ECX=1) could for instance return 201h in ECX, meaning that this is a core-type level, and 4 in EBX because there are 4 logical processors in the package; EAX returned could be any value greater than 3, because it so happens that bit number 2 is used to identify the core in the x2APIC id. Note that bit number 1 of the x2APIC id is not used in this example. However EAX returned at this level could well be 4 (and it happens to be so on a Clarkdale Core i3 5x0) because that also gives a unique id at the package level (=0 obviusly) when shifting the x2APIC id by 4 bits. Finally, you may wonder what the EAX=4 leaf can tell us that we didn't find out already. In EAX[31:26] it returns the APIC mask bits reserved for a package; that would be 111b in our example because bits 0 to 2 are used for identifying logical processors inside this package, but bit 1 is also reserved although not used as part of the logical processor identification scheme. In other words, APIC ids 0 to 7 are reserved for the package, even though half of these values don't map to a logical processor.
The cache hierarchy of the processor is explored by looking at the sub-leaves of leaf 4. The APIC ids are also used in this hierarchy to convey information about how the different levels of cache are shared by the SMT units and cores. To continue our example, the L2 cache, which is shared by SMT units of the same core but not between physical cores on the Westmere is indicated by EAX[26:14] being set to 1, while the information that the L3 cache is shared by the whole package is indicated by setting those bits to (at least) 111b. The cache details, including cache type, size, and associativity are communicated via the other registers on leaf 4.
Beware that older versions of the Intel app note 485 contain some misleading information, particularly with respect to identifying and counting cores in a multi-core processor;[13] errors from misinterpreting this information have even been incorporated in the Microsoft sample code for using cpuid, even for the 2013 edition of Visual Studio,[14] and also in the sandpile.org page for CPUID,[15] but the Intel code sample for identifying processor topology[11] has the correct interpretation, and the current Intel Software Developer’s Manual has more clear language. The (open source) cross-platform production code[16] from Wildfire Games also implements the correct interpretation of the Intel documentation.
Topology detection examples involving older (pre-2010) Intel processors that lack x2APIC (thus don't implement the EAX=Bh leaf) are given in a 2010 Intel presentation.[17] Beware that using that older detection method on 2010 and newer Intel processors may overestimate the number of cores and logical processors because the old detection method assumes there are no gaps in the APIC id space, and this assumption is violated by some newer processors (starting with the Core i3 5x0 series), but these newer processors also come with an x2APIC, so their topology can be correctly determined using the EAX=Bh leaf method.
EAX=7, ECX=0: Extended Features[edit]
This returns extended feature flags in EBX, ECX, and EDX.
Bit | EBX | ECX | ||
---|---|---|---|---|
Short | Feature | Short | Feature | |
0 | fsgsbase | Access to base of %fs and %gs | prefetchwt1 | PREFETCHWT1 instruction |
1 | IA32_TSC_ADJUST | avx512vbmi | AVX-512 Vector Bit Manipulation Instructions | |
2 | sgx | Software Guard Extensions | umip | User-mode Instruction Prevention |
3 | bmi1 | Bit Manipulation Instruction Set 1 | pku | Memory Protection Keys for User-mode pages |
4 | hle | Transactional Synchronization Extensions | ospke | PKU enabled by OS |
5 | avx2 | Advanced Vector Extensions 2 | (reserved) | |
6 | (reserved) | avx512vbmi2 | AVX-512 Vector Bit Manipulation Instructions 2 | |
7 | smep | Supervisor Mode Execution Prevention | (reserved) | |
8 | bmi2 | Bit Manipulation Instruction Set 2 | gfni | Galois Field instructions |
9 | erms | Enhanced REP MOVSB/STOSB | vaes | Vector AES instruction set (VEX-256/EVEX) |
10 | invpcid | INVPCID instruction | vpclmulqdq | CLMUL instruction set (VEX-256/EVEX) |
11 | rtm | Transactional Synchronization Extensions | avx512vnni | AVX-512 Vector Neural Network Instructions |
12 | pqm | Platform Quality of Service Monitoring | avx512bitalg | AVX-512 BITALG instructions |
13 | FPU CS and FPU DS deprecated | (reserved) | ||
14 | mpx | Intel MPX (Memory Protection Extensions) | avx512vpopcntdq | AVX-512 Vector Population Count Double and Quad-word |
15 | pqe | Platform Quality of Service Enforcement | (reserved) | |
16 | avx512f | AVX-512 Foundation | (reserved) | |
17 | avx512dq | AVX-512 Doubleword and Quadword Instructions | mawau | The value of userspace MPX Address-Width Adjust used by the BNDLDX and BNDSTX Intel MPX instructions in 64-bit mode |
18 | rdseed | RDSEED instruction | ||
19 | adx | Intel ADX (Multi-Precision Add-Carry Instruction Extensions) | ||
20 | smap | Supervisor Mode Access Prevention | ||
21 | avx512ifma | AVX-512 Integer Fused Multiply-Add Instructions | ||
22 | pcommit | PCOMMIT instruction | rdpid | Read Processor ID |
23 | clflushopt | CLFLUSHOPT instruction | (reserved) | |
24 | clwb | CLWB instruction | (reserved) | |
25 | intel_pt | Intel Processor Trace | (reserved) | |
26 | avx512pf | AVX-512 Prefetch Instructions | (reserved) | |
27 | avx512er | AVX-512 Exponential and Reciprocal Instructions | (reserved) | |
28 | avx512cd | AVX-512 Conflict Detection Instructions | (reserved) | |
29 | sha | Intel SHA extensions | (reserved) | |
30 | avx512bw | AVX-512 Byte and Word Instructions | sgx_lc | SGX Launch Configuration |
31 | avx512vl | AVX-512 Vector Length Extensions | (reserved) |
Bit | EDX | |
---|---|---|
Short | Feature | |
0 | (reserved) | |
1 | (reserved) | |
2 | avx512_4vnniw | AVX-512 4-register Neural Network Instructions |
3 | avx512_4fmaps | AVX-512 4-register Multiply Accumulation Single precision |
4 | (reserved) | |
5 | (reserved) | |
6 | (reserved) | |
7 | (reserved) | |
8 | (reserved) | |
9 | (reserved) | |
10 | (reserved) | |
11 | (reserved) | |
12 | (reserved) | |
13 | (reserved) | |
14 | (reserved) | |
15 | (reserved) | |
16 | (reserved) | |
17 | (reserved) | |
18 | pconfig | Platform configuration (Memory Encryption Technologies Instructions) |
19 | (reserved) | |
20 | (reserved) | |
21 | (reserved) | |
22 | (reserved) | |
23 | (reserved) | |
24 | (reserved) | |
25 | (reserved) | |
26 | spec_ctrl, part of Indirect Branch Control (IBC) | Speculation Control: Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Prediction Barrier (IBPB)[18][19] |
27 | part of Indirect Branch Control (IBC) | Single Thread Indirect Branch Predictor (STIBP)[18] |
28 | (reserved) | |
29 | IA32_ARCH_CAPABILITIES MSR[18] | |
30 | (reserved) | |
31 | Speculative Store Bypass Disable (SSBD),[18] as mitigation for Speculative Store Bypass |
EAX=80000000h: Get Highest Extended Function Implemented[edit]
The highest calling parameter is returned in EAX.
EAX=80000001h: Extended Processor Info and Feature Bits[edit]
This returns extended feature flags in EDX and ECX.
AMD feature flags are as follows:[20][21]
Bit | EDX | ECX | ||
---|---|---|---|---|
Short | Feature | Short | Feature | |
0 | fpu | Onboard x87 FPU | lahf_lm | LAHF/SAHF in long mode |
1 | vme | Virtual mode extensions (VIF) | cmp_legacy | Hyperthreading not valid |
2 | de | Debugging extensions (CR4 bit 3) | svm | Secure Virtual Machine |
3 | pse | Page Size Extension | extapic | Extended APIC space |
4 | tsc | Time Stamp Counter | cr8_legacy | CR8 in 32-bit mode |
5 | msr | Model-specific registers | abm | Advanced bit manipulation (lzcnt and popcnt) |
6 | pae | Physical Address Extension | sse4a | SSE4a |
7 | mce | Machine Check Exception | misalignsse | Misaligned SSE mode |
8 | cx8 | CMPXCHG8 (compare-and-swap) instruction | 3dnowprefetch | PREFETCH and PREFETCHW instructions |
9 | apic | Onboard Advanced Programmable Interrupt Controller | osvw | OS Visible Workaround |
10 | (reserved) | ibs | Instruction Based Sampling | |
11 | syscall | SYSCALL and SYSRET instructions | xop | XOP instruction set |
12 | mtrr | Memory Type Range Registers | skinit | SKINIT/STGI instructions |
13 | pge | Page Global Enable bit in CR4 | wdt | Watchdog timer |
14 | mca | Machine check architecture | (reserved) | |
15 | cmov | Conditional move and FCMOV instructions | lwp | Light Weight Profiling[22] |
16 | pat | Page Attribute Table | fma4 | 4 operands fused multiply-add |
17 | pse36 | 36-bit page size extension | tce | Translation Cache Extension |
18 | (reserved) | |||
19 | mp | Multiprocessor Capable | nodeid_msr | NodeID MSR |
20 | nx | NX bit | (reserved) | |
21 | (reserved) | tbm | Trailing Bit Manipulation | |
22 | mmxext | Extended MMX | topoext | Topology Extensions |
23 | mmx | MMX instructions | perfctr_core | Core performance counter extensions |
24 | fxsr | FXSAVE, FXRSTOR instructions, CR4 bit 9 | perfctr_nb | NB performance counter extensions |
25 | fxsr_opt | FXSAVE/FXRSTOR optimizations | (reserved) | |
26 | pdpe1gb | Gibibyte pages | dbx | Data breakpoint extensions |
27 | rdtscp | RDTSCP instruction | perftsc | Performance TSC |
28 | (reserved) | pcx_l2i | L2I perf counter extensions | |
29 | lm | Long mode | (reserved) | |
30 | 3dnowext | Extended 3DNow! | (reserved) | |
31 | 3dnow | 3DNow! | (reserved) |
EAX=80000002h,80000003h,80000004h: Processor Brand String[edit]
These return the processor brand string in EAX, EBX, ECX and EDX.
CPUID
must be issued with each parameter in sequence to get the entire 48-byte null-terminated ASCII processor brand string.[23] It is necessary to check whether the feature is present in the CPU by issuing CPUID
with EAX = 80000000h
first and checking if the returned value is greater or equal to 80000004h.EAX=80000005h: L1 Cache and TLB Identifiers[edit]
This function contains the processor’s L1 cache and TLB characteristics.
EAX=80000006h: Extended L2 Cache Features[edit]
Returns details of the L2 cache in ECX, including the line size in bytes, type of associativity (encoded by a 4 bits) and the cache size.
EAX=80000007h: Advanced Power Management Information[edit]
This function provides advanced power management feature identifiers.
EAX=80000008h: Virtual and Physical address Sizes[edit]
Returns largest virtual and physical address sizes in EAX.Bits 07-00: #Physical Address Bits.Bits 15-8: #Linear Address Bits.Bits 31-16: Reserved = 0.It could be used by the hypervisor in a virtual machine system to report physical/virtual address sizes possible with the virtual CPU.
EAX=8FFFFFFFh: AMD Easter Egg[edit]
Specific to AMD K7 and K8 CPUs, this returns the string 'IT'S HAMMER TIME' in EAX, EBX, ECX and EDX.[24]
CPUID usage from high-level languages[edit]
This information is easy to access from other languages as well. For instance, the C code for gcc below prints the first five values, returned by the cpuid:
Or, a generally useful C implementation that works on 32- and 64-bit systems:
GCC also provides a header called
<cpuid.h>
on systems that have CPUID. The __cpuid
is a macro expanding to inline assembly. Typical usage would be:But if one requested an extended feature not present on this CPU, they would not notice and might get random, unexpected results. Safer version is also provided in
<cpuid.h>
. It checks for extended features and does some more safety checks. The output values are not passed using reference-like macro parameters, but more conventional pointers.Notice the ampersands in
&a, &b, &c, &d
and the conditional statement. If the __get_cpuid
call receives a correct request, it will return a non-zero value, if it fails, zero.[25]Microsoft Visual C compiler has builtin function
__cpuid()
so the cpuid instruction may be embedded without using inline assembly, which is handy since the x86-64 version of MSVC does not allow inline assembly at all. The same program for MSVC would be:For Borland/Embarcadero C compilers (bcc32), native asm function calls are necessary, as there is no asm() implementation. The pseudo code:
Many interpreted or compiled scripting languages are capable of using CPUID via an FFI library. One such implementation shows usage of the Ruby FFI module to execute assembly language that includes the CPUID opcode.
CPU-specific information outside x86[edit]
Some of the non-x86 CPU architectures also provide certain forms of structured information about the processor's abilities, commonly as a set of special registers:
![1960-9db 1960-9db](/uploads/1/2/6/6/126609005/500284942.jpg)
- ARM architectures have a
CPUID
coprocessor register which requires EL1 or above to access.[26] - The IBM System z mainframe processors have a Store CPU ID (
STIDP
) instruction since the 1983 IBM 4381[27] for querying the processor ID.[28] - The MIPS32/64 architecture defines a mandatory Processor Identification (
PrId
) and a series of daisy-chained Configuration Registers.[29] - The PowerPC processor has the 32-bit read-only Processor Version Register (
PVR
) identifying the processor model in use. The instruction requires supervisor access level.[30]
DSP and transputer-like chip families have not taken up the instruction in any noticeable way, in spite of having (in relative terms) as many variations in design. Alternate ways of silicon identification might be present; for example, DSPs from Texas Instruments contain a memory-based register set for each functional unit that starts with identifiers determining the unit type and model, its ASIC design revision and features selected at the design phase, and continues with unit-specific control and data registers. Access to these areas is performed by simply using the existing load and store instructions; thus, for such devices there is no need for extending the register set for the device identification purposes.[citation needed]
See also[edit]
Motorola Vip 1960-9db 256 Manual Download
- CPU-Z, a Windows utility that uses
CPUID
to identify various system settings - Speculative Store Bypass (SSB)
- /proc/cpuinfo, a text file generated by certain systems containing some of the CPUID information
References[edit]
- ^'Intel 64 and IA-32 Architectures Software Developer's Manual'(PDF). Intel.com. Retrieved 2013-04-11.
- ^'Detecting Intel Processors - Knowing the generation of a system CPU'. Rcollins.org. Retrieved 2013-04-11.
- ^'LXR linux-old/arch/i386/kernel/head.S'. Lxr.linux.no. Archived from the original on 2012-07-13. Retrieved 2013-04-11.
- ^'CPUID, EAX=4 - Strange results (Solved)'. Software.intel.com. Retrieved 2014-07-10.
- ^'Chapter 3 Instruction Set Reference, A-L'(PDF). Intel® 64 and IA-32 Architectures Software Developer's Manual. Intel Corporation. 2018-12-20. Retrieved 2018-12-20.
- ^http://bochs.sourceforge.net/techspec/24161821.pdf
- ^Huggahalli, Ram; Iyer, Ravi; Tetrick, Scott (2005). 'Direct Cache Access for High Bandwidth Network I/O'. ACM SIGARCH Computer Architecture News. 33 (2): 50–59. doi:10.1145/1080695.1069976. CiteSeerX:10.1.1.91.957.
- ^Drepper, Ulrich (2007), What Every Programmer Should Know About Memory, CiteSeerX:10.1.1.91.957
- ^'Mechanisms to determine if software is running in a VMware virtual machine'. VMware Knowledge Base. VMWare. 2015-05-01.
Intel and AMD CPUs have reserved bit 31 of ECX of CPUID leaf 0x1 as the hypervisor present bit. This bit allows hypervisors to indicate their presence to the guest operating system. Hypervisors set this bit and physical CPUs (all existing and future CPUs) set this bit to zero. Guest operating systems can test bit 31 to detect if they are running inside a virtual machine.
- ^Kataria, Alok; Hecht, Dan (2008-10-01). 'Hypervisor CPUID Interface Proposal'. LKML Archive on lore.kernel.org. Archived from the original on 2019-03-15.
Bit 31 of ECX of CPUID leaf 0x1. This bit has been reserved by Intel & AMD for use by hypervisors, and indicates the presence of a hypervisor. Virtual CPU's (hypervisors) set this bit to 1 and physical CPU's (all existing and future cpu's) set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine.
- ^ abShih Kuo (Jan 27, 2012). 'Intel® 64 Architecture Processor Topology Enumeration'.
- ^'Processor and Core Enumeration Using CPUID | AMD'. Developer.amd.com. Archived from the original on 2014-07-14. Retrieved 2014-07-10.
- ^'Sandybridge processors report incorrect core number?'. Software.intel.com. 2012-12-29. Retrieved 2014-07-10.
- ^'cpuid, __cpuidex'. Msdn.microsoft.com. 2014-06-20. Retrieved 2014-07-10.
- ^'x86 architecture - CPUID'. sandpile.org. Retrieved 2014-07-10.
- ^'topology.cpp in ps/trunk/source/lib/sysdep/arch/x86_x64 – Wildfire Games'. Trac.wildfiregames.com. 2011-12-27. Retrieved 2014-07-10.
- ^Hyper-Threading Technology and Multi-Core Processor Detection
- ^ abcd'Speculative Execution Side Channel Mitigations'(PDF). Revision 2.0. Intel. May 2018 [January 2018]. Document Number: 336996-002. Retrieved 2018-05-26.
- ^'IBRS patch series [LWN.net]'.
- ^CPUID Specification(PDF), AMD, September 2010, retrieved 2013-04-02
- ^Linux kernel source code
- ^Lightweight Profiling Specification(PDF), AMD, August 2010, retrieved 2013-04-03
- ^'Intel® Processor Identification and the CPUID Instruction'(PDF). Download.intel.com. 2012-03-06. Retrieved 2013-04-11.
- ^Ferrie, Peter. 'Attacks on Virtual Machine Emulators'(PDF). symantec.com. Symantec Advanced Threat Research. Retrieved 15 March 2017.
- ^https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/i386/cpuid.h[permanent dead link]
- ^'ARM Information Center'. Infocenter.arm.com. Retrieved 2013-04-11.
- ^'Processor version codes and SRM constants'. Archived from the original on 2014-09-08. Retrieved 2014-09-08.
- ^'IBM System z10 Enterprise Class Technical Guide'(PDF).
- ^'MIPS32 Architecture For Programmers, Volume III: The MIPS32 Privileged Resource Architecture'(PDF). MIPS Technologies, Inc. 2001-03-12.
- ^'PowerPC Operating Environment Architecture, book III'(PDF).
Motorola Vip 1960-9db 256 Manual Pdf
Further reading[edit]
- 'AMD64 Technology Indirect Branch Control Extension'(PDF) (White paper). Revision 4.10.18. Advanced Micro Devices, Inc. (AMD). 2018. Archived(PDF) from the original on 2018-05-09. Retrieved 2018-05-09.
External links[edit]
According to this note, the former Intel app note 485, which was specifically about CPUID, is now incorporated in the Intel® 64 and IA-32 Architectures Software Developer’s Manual. As of July 2014 the manual however still directs the reader to the app note 485 for further information. The latest published version of the app note 485, dating to May 2012, is available via archive.org. App note 485 contains some information that can be and was easily misinterpreted though, particularly with respect to processor topology identification.
The big Intel manuals tend to lag behind the Intel ISA document, available at the top of this page, which is updated even for processors not yet publicly available, and thus usually contains more CPUID bits. For example, as of this writing the ISA book (at revision 19, dated May 2014) documents the CLFLUSHOPT bit in leaf 7, but the big manuals although apparently more up-to-date (at revision 51, dated June 2014) don't mention it.
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